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HANBit
HSD2M64B2
Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V Part No. HSD2M64B2 GENERAL DESCRIPTION
The HSD2M64B2 is a 2M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of two CMOS 512K x 32 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD2M64B2 is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification HSD2M64B2-F/10 :100MHz HSD2M64B2-F/8 :125MHz * F : Auto Self-Refresh with Low Power * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * JEDEC standard 144-Pin SO-DIMM * All inputs are sampled at the positive going edge of the system clock * The used device is 512Kx32Bitx4Banks SDRAM
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HSD2M64B2
PIN ASSIGN
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Symbol Vss DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 Vss DQM0 DQM1 VDD A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 VDD DQ12 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Symbol Vss DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 Vss DQM4 DQM5 VDD A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 VDD DQ44 PIN 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 Symbol DQ13 DQ14 DQ15 Vss NC NC CLK0 VDD /RAS /WE /CS0 NC DU Vss NC NC VDD DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 PIN 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Symbol DQ45 DQ46 DQ47 Vss NC NC CKE0 VDD /CAS NC NC NC CLK1 Vss NC NC VDD DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 PIN 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Symbol DQ22 DQ23 VDD A6 A8 Vss A9 A10_AP VDD DQM2 DQM3 Vss DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 Vss SDA VDD PIN 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Symbol DQ54 DQ55 VDD A7 BA0 Vss BA1 A11 VDD DQM6 DQM7 Vss DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 Vss SCL VDD
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FUNCTIONAL BLOCK DIAGRAM
HSD2M64B2
DQ0-63
CKE0 /CA
CKE CAS RAS CE CKE CAS RAS CE CKE CAS RAS CE CLK DQ0-7,DQ32-39 DQM0 WE A0-A11 BA0-1 DQM4 CLK DQ8-15,DQ40-47 DQM1 WE A0-A11 BA0-1 DQM5 CLK DQ16-23,DQ48-55 DQM2 WE A0-A12 BA0-1 DQM6
U1
CLK0A DQM0 DQM4
/RAS
/CS0
U2
DQM1 DQM5 CLK0B DQM2 DQM6
U3
CKE CAS RAS CE
U4
CLK DQ24-31,DQ56-63 DQM3
DQM3 DQM7
WE A0-A11 BA0-1 DQM7
/WE A0 - A11 BA0-1
Vcc
Two 0.1uF Capacitors per each SDRAM
Vss
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PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable CLK, CKE and DQM Input Function Active on the positive going edge to sample all inputs.
HSD2M64B2
Disables or enables device operation by masking or enabling all inputs except
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. CKE Clock enable Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. A0 ~ A11 Address Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. BA0 ~ BA1 Bank select address Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. /RAS Row address strobe Enables row access & precharge. Column address /CAS strobe /WE Write enable Latches data in starting from CAS, WE active. Data input/output DQM0 ~ 7 mask DQ0 ~ 63 VDD/VSS supply/ground Data input/output Power Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Makes data output Hi-Z, tSHZ after the clock and masks the output. Enables column access. Enables write operation and row precharge. Latches column addresses on the positive going edge of the CLK with CAS low.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature
SYMBOL VIN ,OUT Vcc PD TSTG
RATING -1V to 4.6V -1V to 4.6V 2W -55oC to 150oC
Short Circuit Output Current IOS 100mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HSD2M64B2
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, DQM Address DQ (DQ0 ~ DQ31) SYMBOL CCLK CIN CADD COUT MIN 2.5 2.5 2.5 4.0 MAX 4.0 4.5 4.5 6.5 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) Precharge standby current in non power-down mode ICC2N CS* VIH(min), tCC=10ns mA 20 2 mA 2 mA 130 115 mA 2 -8 -10 VERSION UNIT NOTE
Precharge standby current in power-down mode
ICC2PS
Input signals are changed one time during 20ns
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CKE VIH(min) ICC2NS CLK VIL(max), tCC= 10
HSD2M64B2
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 30 mA 3 mA 3
power-down mode
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
20
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 150 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current ICC5 ICC6 tRC tRC(min) CKE 0.2V 160 2 450 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 150 mA mA mA 5 3 130 mA 2
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V Ns V
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HSD2M64B2
+3.3V
Vtt=1.4V
1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA DOUT Z0=50
50 50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -8 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -10 2 2 2 5 100 9 2 1 1 1 2 ea 7 ns ns ns ns ns ns CLK CLK CLK CLK 2 3 3 6
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2.5 2 2 3 4
tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .
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HSD2M64B2
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -8 PARAMETER CLK cycle time CAS 8 latency=3 tCC CAS 10 latency=2 CLK to valid output delay CAS 6 latency=3 tSAC CAS 6 latency=2 Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 6 latency=3 tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. 6 8 ns 6 ns 2 tOH tCH tCL tSS tSH tSLZ 2.5 3 3 2 1 1 2.5 3.5 3.5 2.5 1 1 ns ns ns ns ns ns 2 3 3 3 3 3 8 ns 1,2 6 12 1000 1000 ns 1 10 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX -10 UNIT NOTE
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HSD2M64B2
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refres h Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X 7 V X L H X precharge precharge H X L H L L X V H X X precharge Entry Exit CKE n-1 H H L H CKE N X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address L H X L H L H X V H Column Address (A0 ~ A9) Column L Address (A0 ~ A9) 4,5 6 4 4,5 4 A9~A0 NOTE 1,2 3 3 3 3
Bank active & row addr. Read & column address precharge
Write & column address
Clock suspend or active power down
Precharge down mode DQM
power
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
HSD2M64B2
PACKAGING INFORMATION
Unit : mm
2.54 mm 0.25 mm MAX
MIN
1.0+ 0.1 mm Gold: 1.04 0.10 mm 1.27 mm Solder: 0.914 0.10 mm
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number
Density
Org.
Package 144 Pin SO-DIMM 144 Pin SO-DIMM 144 Pin SO-DIMM 144 Pin SO-DIMM
Ref.
Vcc
Feature
MAX.frq
HMD2M64B2-10 HMD2M64B2-F10 HMD2M64B2-8 HMD2M64B2-F8
16MByte 16MByte 16MByte 16MByte
2Mx 64 2Mx 64 2Mx 64 2Mx 64
4K 4K 4K 4K
3.3V 3.3V 3.3V 3.3V Low Power Low Power
100MHz 100MHz 125MHz 125MHz
* F : Auto Self-Refresh with Low Power
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